1. Field of the Invention
The disclosed technology generally relates to semiconductor devices, and more particularly to spin transfer torque magnetic random access memory (STTMRAM) elements having perpendicular magnetic anisotropy (PMA).
2. Description of the Related Technology
Magnetic random access memory (MRAM) is emerging as an alternative to conventional semiconductor memories such as SRAM, DRAM and/or flash memory. Compared to volatile memories such as SRAM and DRAM, MRAM can be advantageous because it can be non-volatile. Compared to non-volatile memories such as flash memory used for storage application, MRAM can be advantageous because it can offer high endurance (e.g., greater than 106 cycles). It has been recognized that, in order to compete with flash memory as a non-volatile memory, there is a need to increase the density of MRAM cells in a chip, which involves keeping the MRAM cells as small as possible. It has also been recognized that, in order to compete with SRAM and DRAM as a volatile memory, there is a need to increase the speed of access without compromising the density.
As compared to field-switchable MRAM devices that were studied in the earlier part of the last decade, spin-torque transfer based MRAMs (STTMRAMs) have gained popularity in part due to their potential to be scaled to very small sizes. It has been recognized that scalability of STTMRAMs can be limited by thermal stability, as well as by writability. Two different geometries—one with magnetization in plane and another with magnetization out-of-plane (perpendicular)—have been proposed. It has been suggested that, while the former may be implemented at entry level, the latter may be more promising to be implemented as a more scalable geometry of the two different geometries of magnetic tunnel junction (MTJ) cells, especially from switching and thermal stability perspectives.
Some STTMRAM devices comprise a magnetic tunnel junction (MTJ) element, which includes a tunnel barrier layer sandwiched between a reference layer and a storage layer. Several material systems have been proposed and utilized. For example, a perpendicular MTJ stack structure such as CoFeB/MgO/CoFeB in which a single layer of CoFeB having perpendicular magnetic anisotropy (PMA) can be used in both storage layer and reference layer. This work was introduced by Tohoku university group and it was published with the title of “A perpendicular-anisotropy CoFeB—MgO magnetic tunnel junction” by S. Ikeda et al. in Nature Materials 9, page 721 (2010). This stack structure has been demonstrated for STTMRAM device application. Because it is based on the standard CoFeB—MgO structure, high tunnel magnetoresistance (TMR) signal, low switching current density (Jc) and appreciable PMA can be achieved simultaneously. In a first demonstrated CoFeB—MgO structure, switching fields of storage layer and reference layer are separated by slightly changing the CoFeB thickness. However, such stack design requires a thinner reference layer and results in less Jc margin for reference layer switching.
In order to increase the stability of the reference layer, D. C. Worldege et al. proposed in Applied Physical Letters 98, 022501 (2011) using a synthetic antiferromagnetic (SAF) coupling structure in the hard layer, in which Co/Pd bilayers are used in the pinned layer. Although the hard layer stability was solved in their experiments, however, some more challenges were identified in their report. First, the Gilbert damping constant in the Pd or Pt in Co-based multilayer stack was high. This was due to a strong spin-orbit coupling between Pd and Pt with Co in such multilayers stack. Second, Pd or Pt in these Co-based multilayer stacks are known as challenging materials to integrate into CMOS processes, especially from etching point of view. Third, the maximum temperature which this material stack can withstand is not reported to be higher than 300° C. Consequently, this material stack cannot be implemented in real MTJ cells being used in STTMRAM devices.
There is thus a need for improvement in material compatibility with CMOS process technology, thermal stability and electrical properties of the STTMRAM device.